UPSD3354DV-40U6 Datasheet, PDF (181/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
Table 116. CSIOP registers and their Offsets (in hexadecimal (continued)
Register
name
Port A
(80-
pin)
Port B
Port C
Port D
Other
Description
Link
Drive Select
08h
09h
16h
17h
Write to configure port pins as either
CMOS push-pull or Open Drain on
some pins, while selecting high slew
rate on other pins. Read to check
status. Default output type is CMOS
push-pull.
Table 146
on
page 217
Input
Macrocells
0Ah 0Bh 18h
Read to obtain logic state of IMCs. No
WRITEs.
Table 127
on
page 206
Enable Out
OCh 0Dh 1Ah
1Bh
Read state of output enable logic on
each I/O port driver. 1 = driver output is
enabled, 0 = driver is off, and it is in
high impedance state. No WRITEs.
Table 150
on
page 217
) _Output
t(s ^Macrocells
AB
uc ^(MCELLAB)
Read logic state of MCELLAB outputs Table 123
20h ^{(bank of eight OMCs).}
on
Write to load MCELLAB flip-flops.
page 204
d _Output
ro Macrocells
P BC
(MCELLBC)
Read logic state of MCELLBC outputs _{Table 124}
21h ^{(bank of eight OMCs).}
on
Write to load MCELLBC flip-flops.
page 204
lete Mask
o _Macrocells
bs ^AB
22h
Write to set mask for MCELLAB. Logic
'1' blocks READs/WRITEs of OMC.
Logic '0' will pass OMC value. Read to
check status.
Table 125
on
page 204
- ^{O Mask}
) Macrocells
t(s ^BC
23h
Write to set mask for MCELLBC. Logic
'1' blocks READs/WRITEs of OMC.
Logic '0' will pass OMC value. Read to
check status.
Table 126
on
page 204
uc Main Flash
d _Sector
ro ^Protection
C0h
Read to determine Main Flash Sector
Protection Setting (non-volatile) that
was specified in PSDsoft Express. No
WRITEs.
Table 119
on
page 193
te ^{P Security Bit}
and
le _Secondary
o _{Flash Sector}
Obs ^Protection
Read to determine if PSD module
C2h
device Security Bit is active (non-
volatile) Logic 1 = device secured. Also
read to determine Secondary Flash
Protection Setting (non-volatile) that
Table 120
on
page 193
was specified in PSDsoft. No WRITEs.
PMMR0
B0h
Power Management register 0. WRITE
and READ.
Table 154
on
page 225
PMMR2
B4h
Power Management register 2. WRITE
and READ.
Table 155
on
page 226
Doc ID 9685 Rev 7
181/272