UPSD3354DV-40U6 Datasheet, PDF (141/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Synchronous peripheral interface (SPI)
24 Synchronous peripheral interface (SPI)
UPSD33xx devices support one serial SPI interface in Master mode only. This is a three- or
four-wire synchronous communication channel, capable of full-duplex operation on 8-bit
serial data transfers. The four SPI bus signals are:
● SPIRxD
Pin P1.5 or P4.5 receives data from the Slave SPI device to the UPSD33xx
● SPITxD
Pin P1.6 or P4.6 transmits data from the UPSD33xx to the Slave SPI device
● SPICLK
Pin P1.4 or P4.4 clock is generated from the UPSD33xx to the SPI Slave device
● SPISEL
Pin P1.7 or P4.7 selects the signal from the UPSD33xx to an individual Slave SPI
device
This SPI interface supports single-Master/multiple-Slave connections. Multiple-Master
) _{connections are not directly supported by the UPSD33xx (no internal logic for collision}
t(s ^detection).
uc ^{If more than one Slave device is required, the SPISEL signal may be generated from}
d UPSD33xx GPIO outputs (one for each Slave) or from the PLD outputs of the PSD module.
ro ^{Figure 40 illustrates three examples of SPI device connections using the UPSD33xx:}
P ● Single-Master/Single-Slave with SPISEL
te ^{● Single-Master/Single-Slave without SPISEL}
Obsolete ^{Product(s) - Obsole ● Single-Master/Multiple-Slave without SPISEL}
Doc ID 9685 Rev 7
141/272