UPSD3354DV-40U6 Datasheet, PDF (212/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
27.4.38 PLD I/O mode
Pins on Ports A, B, C, and D can serve as inputs to either the DPLD or the GPLD. Inputs to
these PLDs from Ports A, B, and C are routed through IMCs before reaching the PLD input
bus. Inputs to the PLDs from Port D do not pass through IMCs, but route directly to the PLD
input bus.
Pins on Ports A, B, and C can serve as outputs from GPLD OMCs, and Port D pins can be
outputs from the DPLD (external chip-selects) which do not consume OMCs.
Whenever a pin is specified to be a PLD output, it cannot be used for MCU I/O mode, or
other pin modes. If a pin is specified to be a PLD input, it is still possible to read the pin using
MCU I/O input mode with the csiop register Data In. Also, the csiop Direction register can
still affect a pin which is used for a PLD input. The csiop Data Out register has no effect on a
PLD output pin.
Each pin on Ports A, B, C, and D have a tri-state buffer at the final output stage. The Output
Enable signal for this buffer is driven by the logical OR of two signals. One signal is an
Output Enable signal generated by the AND-OR array (from an .oe equation specified in
Obsolete ^{Product(s) - Obsolete Product(s) Note:}
PSDsoft), and the other signal is the output of the csiop Direction register. This logic is
shown in Figure 68 on page 208. At power-on, all port pins default to high-impedance input
(Direction registers default to 00h). However, if an equation is written for the Output Enable
that is active at power-on, then the pin will behave as an output.
PLD I/O equations are specified in PSDsoft Express and programmed into the UPSD using
JTAG. Figure 69 shows a very simple combinatorial logic example which is implemented on
pins of Port B.
To give a general idea how PLD logic is implemented using PSDsoft Express, Figure 70 on
page 213 illustrates the pin declaration window of PSDsoft Express, showing the PLD
output at pin PB0 declared as “Combinatorial” in the “PLD Output” section, and a signal
name, “pld_out”, is specified. The other three signals on pins PB1, PB2, and PB3 would be
declared as “Logic or Address” in the “PLD Input” section, and given signal names.
In the “Design Assistant” window of PSDsoft Express shown in Figure 71 on page 214,
simply enter the logic equation for the signal “pld_out” as shown. Either type in the logic
statements or enter them using a point-and-click method, selecting various signal names
and logic operators available in the window.
After PSDsoft Express has accepted and realized the logic from the equations, it
synthesizes the logic statement:
pld_out = ( pld_in_1 # pld_in_2 ) & !pld_in_3;
to be programmed into the GPLD. See the PSDsoft User’s Manual for all the steps.
If a particular OMC output is specified as an internal node and not specified as a port pin
output in PSDsoft Express, then the port pin that is associated with that OMC can be used
for other I/O functions.
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