UPSD3354DV-40U6 Datasheet, PDF (56/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Dual data pointers
11 Dual data pointers
UPSD33xx
XDATA is accessed by the External Direct addressing mode, which uses a 16-bit address
stored in the DPTR register. Traditional 8032 architecture has only one DPTR register. This
is a burden when transferring data between two XDATA locations because it requires heavy
use of the working registers to manipulate the source and destination pointers.
However, the UPSD33xx has two data pointers, one for storing a source address and the
other for storing a destination address. These pointers can be configured to automatically
increment or decrement after each data transfer, further reducing the burden on the 8032
and making this kind of data movement very efficient.
11.1 Data Pointer Control register, DPTC (85h)
By default, the DPTR register of the UPSD33xx will behave no different than in a standard
8032 MCU. The DPSEL0 Bit of SFR register DPTC shown in Table 13 on page 56, selects
which one of the two “background” data pointer registers (DPTR0 or DPTR1) will function as
) _{the traditional DPTR register at any given time. After reset, the DPSEL0 Bit is cleared,}
t(s ^{enabling DPTR0 to function as the DPTR, and firmware may access DPTR0 by reading or}
c writing the traditional DPTR register at SFR addresses 82h and 83h. When the DPSEL0 bit
u _{is set, then the DPTR1 register functions as DPTR, and firmware may now access DPTR1}
d _{through SFR registers at 82h and 83h. The pointer which is not selected by the DPSEL0 bit}
ro _{remains in the background and is not accessible by the 8032. If the DPSEL0 bit is never set,}
P _{then the UPSD33xx will behave like a traditional 8032 having only one DPTR register.}
te _{To further speed XDATA to XDATA transfers, the SFR bit, AT, may be set to automatically}
le toggle the two data pointers, DPTR0 and DPTR1, each time the standard DPTR register is
o _{accessed by a MOVX instruction. This eliminates the need for firmware to manually}
s _{manipulate the DPSEL0 bit between each data transfer.}
Ob Detailed description for the SFR register DPTC is shown in Table 13.
) ^- _{Table 13.}
t(s Bit 7
uc _–
DPTC: Data Pointer Control register (SFR 85h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AT
–
–
–
–
–
DPSEL0
Prod _{Table 14.}
teBit
le ₇
Obso ⁶
DPTC register bit definition
Symbol
R/W
Definition
–
–
Reserved
0 = Manually Select Data Pointer
AT
R,W
1 = Auto Toggle between DPTR0 and DPTR1
5-1
–
–
Reserved
0 = DPTR0 Selected for use as DPTR
0
DPSE0
R,W
1 = DPTR1 Selected for use as DPTR
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Doc ID 9685 Rev 7