UPSD3354DV-40U6 Datasheet, PDF (95/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Standard 8032 timer/counters
period (12 / f_OSC, seconds). However, if MCU_CLK is divided by the SFR CCON0, then the
sample period must be calculated based on the resultant, longer, MCU_CLK frequency. In
this case, an external clock signal on pins C0, C1, or T2 should have a duration longer than
one MCU machine cycle, t_{MACH_CYC}. Section 19.5: Watchdog timer (WDT) on page 90
explains how to estimate t_{MACH_CYC}.
Table 54. TCON: Timer Control register (SFR 88h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Table 55. TCON register bit definition
Bit
Symbol
R/W
Definition
Timer 1 overflow interrupt flag.
7
TF1
R
Set by hardware upon overflow. Automatically cleared by
hardware after firmware services the interrupt for Timer 1.
) ^{Timer 1 run control.}
t(s ⁶
TR1
R,W 1 = Timer/Counter 1 is on,
0 = Timer/Counter 1 is off.
uc _{Timer 0 overflow interrupt flag.}
d ₅
TF0
R
Set by hardware upon overflow. Automatically cleared by
ro _{hardware after firmware services the interrupt for Timer 0.}
P _{Timer 0 run control.}
te ₄
TR0
R,W 1 = Timer/Counter 0 is on,
le _{0 = Timer/Counter 0 is off.}
so Interrupt flag for external interrupt pin, EXTINT1. Set by
b ₃
IE1
R
hardware when edge is detected on pin. Automatically cleared
O ^{by hardware after firmware services EXTINT1 interrupt.}
-_{Trigger type for external interrupt pin EXTINT1.}
t(s) ²
IT1
R,W 1 = falling edge,
0 = low-level
uc Interrupt flag for external interrupt pin, EXTINT0.
rod ¹
IE0
R
Set by hardware when edge is detected on pin. Automatically
cleared by hardware after firmware services EXTINT0
P ^interrupt.
te ^{Trigger type for external interrupt pin EXTINT0.}
le ⁰
IT0
R,W 1 = falling edge,
Obso ^{0 = low-level}
Doc ID 9685 Rev 7
95/272