UPSD3354DV-40U6 Datasheet, PDF (65/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Interrupt system
13.1.8
PCA interrupt
The PCA has eight interrupt sources, which are logically ORed together when interrupting
the MCU.The ISR must read the flag bits to determine the cause of the interrupt.
● Each of the six TCMs can generate a "match or capture" interrupt on flag bits OFV5..0
respectively.
● Each of the two 16-bit counters can generate an overflow interrupt on flag bits INTF1
and INTF0 respectively.
Table 19, Table 18, Table 19, and Table 21 have detailed bit definitions of the interrupt
system SFRs.
Table 19.
Bit 7
EA
IE: Interrupt Enable register (SFR A8h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
–
ET2
ES0
ET1
EX1
ET0
Bit 0
EX0
Table 20. IE register bit definition
t(s) ^Bit
Symbol
R/W
Function
c _{Global disable bit}
du 7
EA
R,W
0 = All interrupts are disabled.
ro ^{1 = Each interrupt source can be individually enabled or}
disabled by setting or clearing its enable bit.
P _{Do not modify this bit. It is used by the JTAG debugger}
te 6
–
R,W for instruction tracing. Always read the bit and write back
le ^{the same bit value when writing this SFR.}
o ₅₍₁₎
ET2
R,W Enable Timer 2 Interrupt
bs ₄(1)
ES0
R,W Enable UART0 Interrupt
O ₃₍₁₎
ET1
R,W Enable Timer 1 Interrupt
) ^- ₂(1)
EX1
R,W Enable External Interrupt INT1
t(s ₁⁽¹⁾
ET0
R,W Enable Timer 0 Interrupt
uc 0⁽¹⁾
EX0
R,W Enable External Interrupt INT0
rod ^{1. 1 = Enable Interrupt, 0 = Disable Interrupt}
P _{Table 21.}
te_{Bit 7}
Obsole ^EADC
IEA: Interrupt Enable Addition register (SFR A7h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ESPI
EPCA
ES1
–
–
EI²C
–
Table 22. IEA register bit definition
Bit
Symbol
R/W
Function
7⁽¹⁾
EADC
R,W
Enable ADC Interrupt
6⁽¹⁾
ESPI
R,W
Enable SPI Interrupt
5⁽¹⁾
EPCA
R,W
Enable Programmable Counter Array Interrupt
Doc ID 9685 Rev 7
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