UPSD3354DV-40U6 Datasheet, PDF (214/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
Figure 71. Using the Design Assistant in PSDsoft Express for simple PLD example
uct(s) _{27.4.39 Latched address output mode}
rod ^{In the MCU module, the data bus Bits D0-D15 are multiplexed with the low address Bits A0-}
A15, and the ALE signal is used to separate them with respect to time. Sometimes it is
P _{necessary to send de-multiplexed address signals to external peripherals or memory}
te _{devices. Latched Address Output mode will drive individual demuxed address signals on}
le pins of Ports A or B. Port pins can be designated for this function on a pin-by-pin basis,
o _{meaning that an entire port will not be sacrificed if only a few address signals are needed.}
bs _{To activate this mode, the desired pins on Port A or Port B are designated as “Latched}
O _{Address Out” in PSDsoft. Then in the 8032 initialization firmware, a logic ’1’ is written to the}
- _{csiop Control register for Port A or Port B in each bit position that corresponds to the pin of}
) _{the port driving an address signal. Table 144 and Table 145 define the csiop Control register}
t(s ^{locations and bit assignments.}
c _{The latched low address byte A4-A7 is available on both Port A and Port B. The high}
du ^{address byte A8-A15 is available on Port B only. Selection of high or low address byte is}
ro ^{specified in PSDsoft Express.}
P _{Table 144. Latched Address output, Port A Control register (address = csiop+offset 02h)(1)(2)(3)}
te _{Bit 7}
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ole _PA7
s_{(addr A7)}
PA6
(addr A6)
PA5
(addr A5)
PA4
(addr A4)
Ob1. Port A not available on 52-pin UPSD33xx devices
PA3
(addr A3)
PA2
(Addr A2)
PA1
(addr A1)
PA0
(addr A0)
2. For each bit, 1 = drive demuxed 8032 address signal on pin, 0 = pin is default mode, MCU I/O
3. Default state for register is 00h after reset or power-up
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Doc ID 9685 Rev 7