UPSD3354DV-40U6 Datasheet, PDF (72/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

Power saving modes
UPSD33xx
Table 29. MCU module port and peripheral status during reduced power modes
Mode
Ports 1,
3, 4
PCA
SPI
I2C
ADC
SUPER ^UART0, TIMER EXT
VISOR _UART1 0,1,2 INT0, 1
Idle
Maintain
Data
Active
Active
Active
Active Active⁽¹⁾ Active
Active
Active
Powe
r-
down
Maintain
Data
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
1. The watchdog timer is not active during Idle mode. Other supervisor functions are active: LVD, external
reset, JTAG debug reset
Table 30. State of 8032 MCU bus Signals during Power-down and Idle modes
Mode
ALE
PSEN_
RD_
WR_
AD0-7
A8-15
Idle
0
1
1
1
FFh
FFh
Power-down
0
1
1
1
FFh
t(s) _{Table 31.}
uc _{Bit 7}
rod ^SMOD0
PCON: Power Control register (SFR 87h, reset value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SMOD1
–
POR
RCLK1 TCLK1
PD
FFh
Bit 0
IDL
te ^P _{Table 32. PCON register bit definition}
le _Bit
Symbol
R/W
Obso ₇
SMOD0
R,W
roduct(s) ^{- 6}
SMOD1
R,W
lete ^P5
–
–
Obso ₄
POR
R,W
Function
Baud Rate Double Bit (UART0)
0 = No Doubling
1 = Doubling
(See Section 21.3: UART baud rates on
page 110 for details.)
Baud Rate Double Bit for 2nd UART
(UART1)
0 = No Doubling
1 = Doubling
(See Section 21.3: UART baud rates on
page 110 for details.)
Reserved
Only a power-on, and a Reset sets this bit
(cold reset). Warm reset will not set this bit.
'0,' Cleared to zero with firmware
'1,' Is set only by a power-on reset generated
by Supervisory circuit (see Section 19.3:
Power-up reset on page 90 for details).
Received Clock Flag (UART1)
3
RCLK1
R,W _{(See Table 58 on page 100 for flag}
description.)
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Doc ID 9685 Rev 7