UPSD3354DV-40U6 Datasheet, PDF (107/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Serial UART interfaces
21.1.3
Mode 2
Mode 2 provides asynchronous, full-duplex communication using a total of 11 bits per data
byte. Data is transmitted through TxD and received through RxD with: a Start Bit (logic '0');
eight data bits (LSB first); a programmable 9th data bit; and a Stop Bit (logic '1'). Upon
Transmit, the 9th data bit (from bit TB8 in SCON) can be assigned the value of '0' or '1.' Or,
for example, the Parity Bit (P, in the PSW) could be moved into TB8. Upon receive, the 9th
data bit goes into RB8 in SCON, while the Stop Bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 of f_OSC.
21.1.4 Mode 3
Mode 3 is the same as mode 2 in all respects except the baud rate is variable like it is in
mode 1.
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in mode 0 by the condition RI = 0 and REN = 1. Reception is
initiated in the other modes by the incoming Start Bit if REN = 1.
) ^{Table 62. UART operating modes}
t(s ^{Bits of SFR,}
c _{Mode Synchronization}
SCON
du ^{SM0 SM1}
Pro ₀
Synchronous
0
0
olete ¹
Asynchronous
0
1
Obs ₂
Asynchronous
1
0
ct(s) ^{- 3}
Asynchronous
1
1
Baud clock
Data
bits
Start/Stop
bits
See figure
f_OSC/12
Figure 27
8
None
on
page 113
Timer 1 or Timer 2
Overflow
8
1 Start, 1
Stop
Figure 29
on
page 115
f_OSC/32 or f_OSC/64
9
1 Start, 1
Stop
Figure 31
on
page 117
Timer 1 or Timer 2
Overflow
9
1 Start, 1
Stop
Figure 33
on
page 118
Obsolete ^{Produ 21.1.5}
Multiprocessor communications
Modes 2 and 3 have a special provision for multiprocessor communications. In these
modes, 9 data bits are received. The 9th one goes into bit RB8, then comes a stop bit. The
port can be programmed such that when the stop bit is received, the UART interrupt will be
activated only if bit RB8 = 1. This feature is enabled by setting bit SM2 in SCON. A way to
use this feature in multi-processor systems is as follows: When the master processor wants
to transmit a block of data to one of several slaves, it first sends out an address byte which
identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in
an address byte and 0 in a data byte. With SM2 = 1, no slave will be interrupted by a data
byte. An address byte, however, will interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and
prepare to receive the data bytes that will be coming. The slaves that were not being
Doc ID 9685 Rev 7
107/272