UPSD3354DV-40U6 Datasheet, PDF (101/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Standard 8032 timer/counters
Table 59. T2CON register bit definition
Bit Symbol R/W
Definition
Counter or Timer function select.
1
C/T2 R,W _{When C/T2 = 0, function is timer, clocked by internal clock. When C/T2}
= 1, function is counter, clocked by signal sampled on external pin, T2.
Capture/Reload.
When CP/RL2 = 1, capture occurs on negative transition at pin T2X if
0
CP/RL2 R,W ^{EXEN2 = 1. When CP/RL2 = 0, auto-reload occurs when Timer 2}
overflows, or on negative transition at pin T2X when EXEN2=1. When
RCLK = 1 or TCLK = 1, CP/RL2 is ignored, and Timer 2 is forced to
auto-reload upon Timer 2 overflow
1. The RCLK1 and TCLK1 Bits in the SFR named PCON control UART1, and have the exact same function
as RCLK and TCLK.
Table 60. Timer/counter 2 operating modes
uct(s) ^Mode
Bits in T2CON SFR
RCLK
or
TCLK
CP/RL2
Pin
T2X
TR2 EXEN2 ⁽¹⁾
Remarks
Input clock
Counter,
Timer, external
internal (pin T2,
P1.0)
Prod 0
16-bit
te Auto-
le ^reload
o ₀
Obs ₀
) ^- _16-bit
t(s ^Capture
0
roduc ¹
Baud Rate
P _Generator
te ¹
le _Off
x
Obso ^{1. ↓ = falling edge}
reload [RCAP2H,
0
1
0
x
RCAP2L] to [TH2, TL2]
upon overflow (up
counting)
reload [RCAP2H,
MAX
f_OSC/12 _fOSC/24
0
1
1
↓ RCAP2L] to [TH2, TL2] at
falling edge on pin T2X
1
1
0
x
16-bit Timer/Counter (up
counting)
1
1
1
Capture [TH2, TL2] and
↓
store to [RCAP2H,
RCAP2L] at falling edge
MAX
f_OSC/12 _fOSC/24
on pin T2X
x
1
0
x
No overflow interrupt
request (TF2)
f_OSC/2 –
x
1
1
↓
Extra Interrupt on pin T2X,
sets TF2
x
0
x
x Timer 2 stops
–
–
Doc ID 9685 Rev 7
101/272