UPSD3354DV-40U6 Datasheet, PDF (39/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
8032 MCU registers
7.7.5
Overflow flag (OV)
The OV flag is set when: an ADD, ADDC, or SUBB instruction causes a sign change; a MUL
instruction results in an overflow (result greater than 255); a DIV instruction causes a divide-
by-zero condition. The OV flag is cleared by the ADD, ADDC, SUBB, MUL, and DIV
instructions in all other cases. The CLRV instruction will clear the OV flag at any time.
7.7.6
Parity flag (P)
The P flag is set if the sum of the eight bits in the Accumulator is odd, and P is cleared if the
sum is even.
Table 4. Register bank select addresses
RS1
RS0
Register bank
8032 internal DATA address
0
0
0
00h - 07h
0
1
1
08h - 0Fh
1
0
2
) ₁
1
3
10h - 17h
18h - 1Fh
uct(s _{Figure 11. Program Status Word (PSW) register}
rod ^MSB
PSW ^{CY AC FO RS1 RS0 OV}
P _{Carry Flag}
te _{Auxillary Carry Flag}
le _{General Purpose Flag}
LSB
P _{Reset Value 00h}
Parity Flag
Bit not assigned
Overflow Flag
bso Register Bank Select Flags
Obsolete ^{Product(s) - O (to select Bank0-3)}
AI06639
Doc ID 9685 Rev 7
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