UPSD3354DV-40U6 Datasheet, PDF (78/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

I/O ports of MCU module
UPSD33xx
Reading port pin vs. reading port latch
When firmware reads the GPIO ports, sometimes the actual port pin is sampled in
hardware, and sometimes the port SFR latch is read and not the actual pin, depending on
the type of MCU instruction used. These two data paths are shown in Figure 16 through
Figure 18 on page 80. SFR latches are read (and not the pins) only when the read is part of
a read-modify-write instruction and the write destination is a bit or bits in a port SFR. These
instructions are: ANL, ORL, XRL, JBC, CPL, INC, DEC, DJNZ, MOV, CLR, and SETB. All
other types of reads to port SFRs will read the actual pin logic level and not the port latch.
This is consistent with 8051 architecture.
Figure 15. MCU module port pin function routing
MCU Module ^Ports
GPIO (8)
SFR
UART0 (2)
8
P3
uct(s) _{ADC (8)}
TIMER0/1 (4)
I2C (2)
GPIO (8)
SFR
Prod _{TIMER2 (2)}
SFR
te UART1 (2)
le ^{SPI (4)}
- ^{Obso PCA (8)}
SFR
GPIO (8)
SFR
8
P1
SFR
8
P4
roduct(s) ^{Low Addr & Data[7:0] 8}
P _{8032 MCU}
te CORE
ole _{Available on PSD 4 Hi Address [15:12]}
Obs^{Module Pins}
Hi Address [11:8]
4
M
C
U
A
D
M
On 80-pin
Devices
C
Only
U
A
C
RD, WR, PSEN, ALE ⁴
N
T
L
AI09199
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Doc ID 9685 Rev 7