UPSD3354DV-40U6 Datasheet, PDF (168/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

PSD module
UPSD33xx
and PSEL1) used to enable a special data bus repeater function on Port A, referred to as
Peripheral I/O mode. There are 69 DPLD input signals which include: 8032 address and
control signals, Page register outputs, PSD module Port pin inputs, and GPLD logic
feedback.
27.1.10
PLD #2, General PLD (GPLD)
This programmable logic is used to create both combinatorial and sequential general
purpose logic (see Figure 64 on page 199). The GPLD contains 16 Output Macrocells
(OMCs) and 20 Input Macrocells (IMCs). Output Macrocell registers are unique in that they
have direct connection to the 8032 data bus allowing them to be loaded and read directly by
the 8032 at runtime through OMC registers in csiop. This direct access is good for making
small peripheral devices (shifters, counters, state machines, etc.) that are accessed directly
by the 8032 with little overhead. There are 69 GPLD inputs which include: 8032 address and
control signals, Page register outputs, PSD module Port pin inputs, and GPLD feedback.
27.1.11 OMCs
There are two banks of eight OMCs inside the GPLD, MCELLAB, and MCELLBC, totalling
) _{16 OMCs all together. Each individual OMC is a base logic element consisting of a flip-flop}
t(s ^{and some AND-OR logic (Figure 65 on page 201). The general structure of the GPLD with}
c _{OMCs is similar in nature to a 22V10 PLD device with the familiar sum-of-products (AND-}
u _{OR) construct. True and compliment versions of 69 input signals are available to the inputs}
d _{of a large AND-OR array. AND-OR array outputs feed into an OR gate within each OMC,}
ro _{creating up to 10 product-terms for each OMC. Logic output of the OR gate can be passed}
P _{on as combinatorial logic or combined with a flip-flop within in each OMC to realize}
te ^{sequential logic. OMC outputs can be used as a buried nodes driving internal feedback to}
le ^{the AND-OR array, or OMC outputs can be routed to external pins on Ports A, B, or C}
o ^{through the OMC Allocator.}
t(s) ^{- Obs 27.1.12}
OMC allocator
The OMC allocator (Figure 66 on page 202) will route eight of the OMCs from MCELLAB to
pins on either Port A or Port B, and will route eight of the OMCs from MCELLBC to pins on
either Port B or Port C, based on what is specified in PSDsoft Express.
uc _27.1.13
Obsolete ^{Prod Note:}
IMCs
Inputs from pins on Ports A, B, and C are routed to IMCs for conditioning (clocking or
latching) as they enter the chip, which is good for sampling and debouncing inputs.
Alternatively, IMCs can pass port input signals directly to PLD inputs without clocking or
latching (Figure 67 on page 205). The 8032 may read the IMCs asynchronously at any time
through IMC registers in csiop.
The JTAG signals TDO, TDI, TCK, and TMS on Port C do not route through IMCs, but go
directly to JTAG logic.
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Doc ID 9685 Rev 7