UPSD3354DV-40U6 Datasheet, PDF (252/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

DC and AC parameters
UPSD33xx
Figure 87. External PSEN/READ cycle (80-pin device only)
tLHLL
tLLPL
ALE
tAVLL
tPLPH
PSEN
RD
MCU
AD0 - AD7
tLLAX
A0-A7
tAZPL
INSTR
IN
tPXAV
tPXIZ
A0-A7
MCU
A8 - A11
tAVIV
A8-A11
tPXIX
A8-A11
AI07875
) _{Table 169. External PSEN or READ cycle AC Characteristics (3 V or 5 V device)}
uct(s ^Symbol
Parameter
40 MHz oscillator⁽¹⁾
Variable oscillator
1/t_CLCL = 8 to 40 MHz _Unit
d _Min
Max
Min
Max
Pro ^tLHLL ^{ALE pulse width}
17
te ^{tAVLL Address setup to ALE}
13
le t_LLAX Address hold after ALE
7.5
so ^tLLPL ^{ALE to PSEN or RD}
7.5
b _{tPLPH PSEN or RD pulse width(2)}
40
) ^{- O tPXIX}
Input instruction/data hold
after PSEN or RD
2
ct(s ^tPHIZ
Input instruction/data float
after PSEN or RD
rodu ^tPXAV
Address hold after PSEN or
RD
7.5
P _tAVIV
Address to valid
instruction/data in⁽²⁾
lete^{tAZPL Address float to PSEN or RD}
–2
o 1. BUSCON register is configured for 4 PFQCLK.
Obs ^{2. Refer to Table 170 for “n” and “m” values.}
t_CLCL – 8
ns
t_CLCL – 12
ns
0.5t_CLCL – 5
ns
0.5t_CLCL – 5
ns
nt_CLCL – 10
ns
2
ns
10.5
0.5t_CLCL – 2 ns
0.5t_CLCL – 5
ns
70
mt_CLCL – 5 ns
–2
ns
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Doc ID 9685 Rev 7