UPSD3354DV-40U6 Datasheet, PDF (128/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

I²C interface
UPSD33xx
23.8 I²C Interface Control register (S1CON)
Table 71.
Bit 7
CR2
Serial Control register S1CON (SFR DCh, Reset Value 00h)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ENI1
STA
STO
ADDR
AA
CR[1:0]
Table 72. S1CON register bit definition
Bit
Symbol
R/W
Function
This bit, along with bits CR1 and CR0, determines the SCL
7
CR2
R,W clock frequency (f_SCL) when SIOE is in Master mode. These
bits create a clock divisor for f_OSC. See Table 73 on page 129.
I²C Interface Enable
6
ENI1
R,W _{0 = SIOE disabled, 1 = SIOE enabled. When disabled, both}
SDA and SCL signals are in high impedance state.
START flag.
) _{When set, Master mode is entered and SIOE generates a}
t(s ^{START condition only if the I2C bus is not busy. When a}
c 5
STA
R,W _{START condition is detected on the bus, the STA flag is}
u _{cleared by hardware. When the STA bit is set during an}
d _{interrupt service, the START condition will be generated after}
ro ^{the interrupt service.}
P _{STOP flag}
te ^{When STO is set in Master mode, the SIOE generates a}
le 4
STO
R,W ^{STOP condition. When a STOP condition is detected, the STO}
flag is cleared by hardware. When the STO bit is set during an
so ^{interrupt service, the STOP condition will be generated after}
b the interrupt service.
O _{This bit is set when an address byte received in Slave mode}
- ₃
ADDR
R,W matches the device address programmed into the S1ADR
) _{register. The ADDR bit must be cleared with firmware.}
t(s _{Assert Acknowledge enable}
c _{If AA = 1, an acknowledge signal (low on SDA) is automatically}
du ^{returned during the acknowledge bit-time on the SCL line}
ro ^{when any of the following three events occur:}
P ^{1. SIOE in Slave mode receives an address that}
matches contents of S1ADR register
te₂
AA
R,W _{2. A data byte has been received while SIOE is in}
le _{Master Receiver mode}
so 3. A data byte has been received while SIOE is a
Ob ^{selected Slave Receiver}
When AA = 0, no acknowledge is returned (high on SDA
during acknowledge bit-time).
These bits, along with bit CR2, determine the SCL clock
1, 0
CR1, CR0
R,W
frequency (f_SCL) when SIOE is in Master mode. These bits
create a clock divisor for f_OSC. See Table 73 on page 129 for
values.
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Doc ID 9685 Rev 7