UPSD3354DV-40U6 Datasheet, PDF (109/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Serial UART interfaces
Table 64.
Bit
1
0
SCON0 register bit definition (continued)
Symbol
R/W
Definition
Transmit Interrupt flag.
TI
R,W ^{Causes interrupt at end of 8th bit time when transmitting in}
mode 0, or at beginning of stop bit transmission in other
modes. Must clear flag with firmware.
Receive Interrupt flag.
RI
R,W ^{Causes interrupt at end of 8th bit time when receiving in mode}
0, or halfway through stop bit reception in other modes (see
SM2 for exception). Must clear this flag with firmware.
Table 65. SCON1: Serial Port UART1 Control register (SFR D8h, reset value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
t(s) Table 66.
Bit
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SCON1 register bit definition
Symbol
R/W
Definition
SM0
Serial Mode Select, See Table 62 on page 107. Important,
notice bit order of SM0 and SM1.
[SM0:SM1] = 00b, mode 0
R,W _{[SM0:SM1] = 01b, mode 1}
[SM0:SM1] = 10b, mode 2
[SM0:SM1] = 11b, mode 3
SM1
SM2
R,W
Serial Multiprocessor Communication Enable.
Mode 0: SM2 has no effect but should remain 0.
R,W ^{Mode 1: If SM2 = 0 then stop bit ignored. SM2 =1 then RI}
active if stop bit = 1.
Mode 2 and 3: Multiprocessor Comm Enable. If SM2=0, 9th
bit is ignored. If SM2=1, RI active when 9th bit = 1.
REN
Receive Enable.
R,W _{If REN=0, UART reception disabled. If REN=1, reception is}
enabled
TB8
R,W
TB8 is assigned to the 9th transmission bit in mode 2 and 3.
Not used in mode 0 and 1.
Mode 0: RB8 is not used.
Mode 1: If SM2 = 0, the RB8 is the level of the received stop
RB8
R,W bit.
Mode 2 and 3: RB8 is the 9th data bit that was received in
mode 2 and 3.
Doc ID 9685 Rev 7
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