UPSD3354DV-40U6 Datasheet, PDF (185/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
PSD module
27.4.3
Reading Flash memory
Under typical conditions, the 8032 may read the Flash memory using READ operations
(READ bus cycles) just as it would a ROM or RAM device. Alternately, the 8032 may use
READ operations to obtain status information about a Program or Erase operation that is
currently in progress. The following sections describe the kinds of READ operations.
27.4.4
Read memory contents
Flash memory is placed in the Read Array mode after Power-up, after a PSD module reset
event, or after receiving a Reset Flash memory instruction sequence from the 8032. The
8032 can read Flash memory contents using standard READ bus cycles anytime the Flash
array is in Read Array mode. Flash memories will always be in Read Array mode when the
array is not actively engaged in a program or erase operation.
27.4.5 Reading the erase/program status bits
The Flash arrays provide several status bits to be used by the 8032 to confirm the
Product(s) ^27.4.6
Obsolete ^{Product(s) - Obsolete 27.4.7}
completion of an erase or program operation on Flash memory, shown in Table 118 on
page 187. The status bits can be read as many times as needed until an operation is
complete.
The 8032 performs a READ operation to obtain these status bits while an erase or program
operation is being executed by the state machine inside each Flash memory array.
Data polling flag (DQ7)
While programming either Flash memory, the 8032 may read the Data Polling Flag Bit
(DQ7), which outputs the complement of the D7 Bit of the byte being programmed into Flash
memory. Once the program operation is complete, DQ7 is equal to D7 of the byte just
programmed into Flash memory, indicating the program cycle has completed successfully.
The correct select signal, FSx or CSBOOTx, must be active during the entire polling
procedure.
Polling may also be used to indicate when an erase operation has completed. During an
erase operation, DQ7 is '0.' After the erase is complete DQ7 is '1.' The correct select signal,
FSx or CSBOOTx, must be active during the entire polling procedure.
DQ7 is valid after the fourth instruction byte WRITE operation (for program instruction
sequence) or after the sixth instruction byte WRITE operation (for erase instruction
sequence).
If all Flash memory sectors to be erased are protected, DQ7 is reset to ’0’ for about 100µs,
and then DQ7 returns to the value of D7 of the previously addressed byte. No erasure is
performed.
Toggle flag (DQ6)
The Flash memories offer an alternate way to determine when a Flash memory program
operation has completed. During the program operation and while the correct sector select
FSx or CSBOOTx is active, the Toggle Flag Bit (DQ6) toggles from '0' to '1' and '1' to ’0’ on
subsequent attempts to read any byte of the same Flash array.
When the internal program operation is complete, the toggling stops and the data read on
the data bus D0-7 is the actual value of the addressed memory byte. The device is now
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