UPSD3354DV-40U6 Datasheet, PDF (126/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

I²C interface
UPSD33xx
23.5.2
Clock sync during handshaking
This allows receivers in different devices to handle various transfer rates, either at the byte-
level, or bit-level.
At the byte-level, a device may pause the transfer between bytes by holding SCL low to have
time to store the latest received byte or fetch the next byte to transmit.
At the bit-level, a Slave device may extend the low period of SCL by holding it low. Thus the
speed of any Master device will adapt to the internal operation of the Slave.
23.6 General call address
A General Call (GC) occurs when a Master-Transmitter initiates a transfer containing a
Slave address of 0000000b, and the R/W bit is logic 0. All Slave devices capable of
responding to this broadcast message will acknowledge the GC simultaneously and then
behave as a Slave-Receiver. The next byte transmitted by the Master will be accepted and
acknowledged by all Slaves capable of handling the special data bytes. A Slave that cannot
handle one of these data bytes must ignore it by not acknowledging it. The I²C specification
) _{lists the possible meanings of the special bytes that follow the first GC address byte, and the}
t(s ^{actions to be taken by the Slave device(s) upon receiving them. A common use of the GC by}
c a Master is to dynamically assign device addresses to Slave devices on the bus capable of a
u _{programmable device address.}
rod ^{The UPSD33xx can generate a GC as a Master-Transmitter, and it can receive a GC as a}
Slave. When receiving a GC address (00h), an interrupt will be generated so firmware may
P _{respond to the special GC data bytes if desired.}
Obsolete ^{Product(s) - Obsolete 23.7}
Serial I/O engine (SIOE)
At the heart of the I²C interface is the hardware SIOE, shown in Figure 39 on page 127. The
SIOE automatically handles low-level I²C bus protocol (data shifting, handshaking,
arbitration, clock generation and synchronization) and it is controlled and monitored by five
SFRs.
The five SFRs shown in Figure 39 on page 127 are:
● S1CON - Interface Control (Table 71 on page 128)
● S1STA - Interface Status (Table 74 on page 130)
● S1DAT - Data Shift register (Table 76 on page 131)
● S1ADR - Device Address (Table 78 on page 131)
● S1SETUP - Sampling Rate (Table 80 on page 132)
126/272
Doc ID 9685 Rev 7