UPSD3354DV-40U6 Datasheet, PDF (161/272 Pages) STMicroelectronics – fast 8032 MCU with programmable logic

UPSD33xx
Programmable counter array (PCA) with PWM
Table 107. PCA Status register PCASTA (SFR 0A5h, Reset Value 00h)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
OVF1
INTF5
INTF4
INTF3
OVF0
INTF2
INTF1
Bit 0
INTF0
Table 108. PCASTA register bit definition
Bit
Symbol
Function
PCA1 Counter OverFlow flag
7
OFV1 ^{Set by hardware when the counter rolls over. OVF1 flags an interrupt if Bit}
EOVFI in PCACON1 is set. OVF1 may be set with either hardware or
software but can only be cleared with software.
TCM5 Interrupt flag
6
INTF5 Set by hardware when a match or capture event occurs.
Must be clear with software.
TCM4 Interrupt flag
5
INTF4 Set by hardware when a match or capture event occurs.
) _{Must be clear with software.}
t(s _{TCM3 Interrupt flag}
uc ⁴
INTF3 Set by hardware when a match or capture event occurs.
d _{Must be clear with software.}
ro _{PCA0 Counter OverFlow flag}
P ₃
OVF0 ^{Set by hardware when the counter rolls over. OVF0 flags an interrupt if Bit}
te ^{EOVFI in PCACON0 is set. OVF1 may be set with either hardware or}
le ^{software but can only be cleared with software.}
o _{TCM2 Interrupt flag}
s ₂
INTF2 Set by hardware when a match or capture event occurs.
b _{Must be clear with software.}
- ^O _{TCM1 Interrupt flag}
) ₁
INTF1 Set by hardware when a match or capture event occurs.
t(s ^{Must be clear with software.}
c_{TCM0 Interrupt flag}
du 0
INTF0 Set by hardware when a match or capture event occurs.
Obsolete ^{Pro Must be clear with software.}
Doc ID 9685 Rev 7
161/272