Z86E3016PSG Datasheet, PDF (98/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
80
Port 3
General Port I/O
Port 3 differs structurally from Port 0, 1, and 2. Port 3 lines are fixed as
four inputs (P33–P30) and four outputs (P37–P34) Port 3 does not have
an input and output register for each bit. Instead, all of the input lines have
one input register, and all of the output lines have an output register. Port
3 can be a CMOS- or TTL- compatible I/O port. Under software control,
the lines can be configured as special control lines for handshake, com-
parator inputs, SPI control, external memory status, or I/O lines for the
on-board serial and timer facilities. Figure 44 is a generic block diagram
of Port 3.
The inputs can be Schmitt-triggered, level-shifted, or single-trip point
buffered. In some cases, the Z8^® MCU may have autolatches hardwired
on certain Port 3 inputs and Low-EMI capabilities on the outputs. Please
refer to specific product specifications for exact input/output buffer type
features. Please refer to the section on counter/timers, Stop-Mode Recov-
ery, serial I/O, comparators, and interrupts for more information on the
relationships of Port 3 to that feature.
I/O Ports
UM001602-0904