Z86E3016PSG Datasheet, PDF (177/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
159
All Z8 devices provide some form of dedicated Stop-Mode Recovery
(SMR) circuitry. Two SMR methods are implemented—a single fixed
input pin or a flexible, programmable set of inputs. The selected Z8
device product specification should be reviewed to determine the SMR
options available for use.
For devices that support SPI, the slave mode compare feature also serves
as a SMR source.
In the simple case, a low level applied to input pin P27 will trigger a
SMR. To use this mode, pin P27 (I/O Port 2, bit 7) must be configured as
an input before STOP mode is entered. The low level on P27 must meet a
minimum pulse width T_WSM. (See the product data sheet) to trigger the
device reset mode). Some Z8 devices provide multiple SMR input
sources. The appropriate SMR source is selected via the SMR Register.
Use of specialized SMR modes (P2.7 input or SMR register based) or the
WDT time-out (only when in STOP mode) provide a unique reset opera-
tion. Some control registers are initialized differently for a SMR/WDT
triggered POR than a standard reset operation. See the product specifica-
tion (register file map) for exact details.
To determine the actual STOP mode current (I_CC2) value for the optional
SMR modes available, see the selected Z8 device’s product data sheet.
STOP mode current (I_CC2) will be minimized when:
• V_CC is at the low end of the devices operating range
• WDT is off in STOP mode
• Output current sourcing is minimized
• All inputs (digital and analog) are at the low or high rail voltages
UM001602-0904
Power-Down Modes