Z86E3016PSG Datasheet, PDF (147/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
129
It is suggested that P31 be configured as an input line by setting P3M
Register bit 5 to 0, although T_IN is still functional if P31 is configured as a
handshake input.
Each High-to-Low transition on T_IN generates an interrupt request IRQ2,
regardless of the selected T_IN mode or the enabled/disabled state of T1.
IRQ2 must therefore be masked or enabled according to the requirements
of the application.
External Clock Input Mode
The T_IN External Clock Input Mode (TMR bit 5 and bit 4 both set to 0)
supports counting of external events, where an event is considered to be a
High-to-Low transition on T_IN (see Figure 82).
See the product data sheet for the minimum allowed T_IN external clock
input period (T_P T_IN).
T_IN
Clock
P3₁
TMR
D₅–D₄ = 00
D
D
PRE1
T1
IRQ₅
Internal
Clock
IRQ₂
Figure 82. External Clock Input Mode
Gated Internal Clock Mode
The T_IN Gated Internal Clock Mode (TMR bit 5 and bit 4 set to 0 and 1
respectively) measures the duration of an external event. In this mode, the
T1 prescaler is driven by the internal timer clock, gated by a High level on
UM001602-0904
Counters and Timers