Z86E3016PSG Datasheet, PDF (148/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
130
T_IN (see Figure 83). T1 counts while T_IN is High and stops counting
while
T_IN is Low. Interrupt request IRQ2 is generated on the High-to-Low tran-
sition of T_IN signalling the end of the gate input. Interrupt request IRQ5 is
generated if T1 reaches its end-of-count.
OSC
÷2
Internal
Clock
TMR
D_5–D_{4 =} 01
÷4
PRE1 T1
IRQ₅
T_IN
P3₁
Gate
DD
IRQ₂
Figure 83. Gated Clock Input Mode
Triggered Input Mode
The T_IN Triggered Input Mode (TMR bits 5 and 4 are set to 1 and 0,
respectively) causes T1 to start counting as the result of an external event
(see Figure 84). T1 is then loaded and clocked by the internal timer clock
following the first High-to-Low transition on the T_IN input. Subsequent
T_IN transitions do not affect T1. In SINGLE-PASS mode, the Enable bit is
reset whenever T1 reaches its end-of-count. Further T_IN transitions will
have no effect on T1 until software sets the Enable Count bit again. In
Continuous mode, once T1 is triggered counting continues until software
resets the Enable Count bit. Interrupt request IRQ5 is generated when T1
reaches its end-of-count.
Counters and Timers
UM001602-0904