Z86E3016PSG Datasheet, PDF (150/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
132
Cascading Counter/Timers
For some applications, it may be necessary to measure a time interval
greater than a single counter/timer can measure. In this case, T_IN and
T_OUT can be used to cascade T0 and T1 as a single unit (see Figure 85).
T0 should be configured to operate in Continuous mode and to drive
T_OUT. T_IN should be configured as an external clock input to T1 and
wired back to T_OUT. On every other T0 end-of-count, T_OUT undergoes a
High-to-Low transition that causes T1 to count.
T1 can operate in either Single-Pass or Continuous mode. When the T1
end-of-count is reached, interrupt request IRQ5 is generated. Interrupt
requests IRQ2 (T_IN High-to-Low transitions) and IRQ4 (T0 end-of-count)
are also generated but are most likely of no importance in this configura-
tion and should be disabled.
OSC
÷2
÷4
PRE0 T0
÷2
P3₆
T_OUT T_IN
P3₁
PRE1 T1
IRQ₅
IRQ₄
IRQ₂
Figure 85. Cascaded Counter/Timers
Reset Conditions
After a hardware reset, the counter/timers are disabled and the contents of
the counter/timer and prescaler registers are undefined. However, the
counting modes are configured for Single-Pass and the T1 clock source is
set for external.
Counters and Timers
UM001602-0904