Z86E3016PSG Datasheet, PDF (111/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
93
1
2
3
4
5
RDY
(Input To Z8)
DAV
(Output From Z8)
Data on Port
(Output From Z8)
Valid Data
State 1.
State 2.
State 3.
State 4.
State 5.
RDY input is High indicating that the I/O device is ready to accept data.
the Z8^® CPU Writes to the port register to initiate a data transfer. Writing to the port outputs new data and
forces DAV Low if and only if RDY is High.
The I/O device forces RDY Low after latching the data. RDY Low causes an interrupt request to be generate
the Z8^® CPU can write new data responses to RDY going Low; however, the data is not output until State 5
The DAV output from the Z8^® CPU is driven High in response to RDY going Low.
The DAV goes High, the I/O device is free to raise RDY High thus returning the interface to its initial state.
Figure 51. Z8 Output Handshake
In applications requiring a strobed signal instead of the interlocked hand-
shake, the Z8^® CPU can satisfy this requirement as follows:
• In the Strobed Input mode, data can be latched in the Port input regis-
ter using the DAV input. The data transfer rate must allow enough
time for the software to read the Port before strobing in the next char-
acter. The RDY output is ignored.
• In the Strobed Output Mode, the RDY input should be tied to the
DAV output.
UM001602-0904
I/O Ports