Z86E3016PSG Datasheet, PDF (68/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
50
(T_POR) before releasing the device out of reset. On these Z8 devices, the
internally generated reset drives the reset pin low for the POR time. Any
devices driving the reset line must be open-drained in order to avoid dam-
age from possible conflict during reset conditions. This reset time allows
the on-board clock oscillator to stabilize.
To avoid asynchronous and noisy reset problems, the Z8^® CPU is
equipped with a reset filter of four external clocks (4TpC). If the external
reset signal is less than 4TpC in duration, no reset occurs. On the fifth
clock after the reset is detected, an internal RST signal is latched and held
for an internal register count of 18 external clocks, or for the duration of
the external reset, whichever is longer. During the reset cycle, DS is held
active low while AS cycles at a rate of the internal system clock. Program
execution begins at location 000Ch, 5-10 TpC cycles after RESET is
released. For the internal Power-On Reset, the reset output time is speci-
fied as T_POR. Please refer to specific product specifications for actual val-
ues.
RESET
1K
1 µF
10 V
+5V
100 KΩ
to
200 KΩ
Figure 23. Example of External Power-On Reset Circuit
Reset
UM001602-0904