Z86E3016PSG Datasheet, PDF (231/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
213
ASM: ADD 43h,
OBJ: 04
08
08h (ADD dst, src)
43 (OPC src, dst)
In general, whenever an instruction format requires an 8-bit register
address, that address can specify any register location in the range 0–255
or a Working Register R0–R15. If, in the above example, register 08h is a
Working Register, the assembly syntax and resulting object code would
be:
ASM: ADD 43h,
OBJ: 04
08
08h (ADD dst, src)
43 (OPC src, dst)
See the device product specification to determine the exact register file
range available. The register file size varies by device type.
Z8 Instruction Summary
Table 39. Summary of Z8 Instruction Set
Instruction and
Operation
ADC dst, src
dst ← dst + src +C
Address
Mode
dst src
Op Code
Byte
(Hex)
Flags Affected
C Z S VDH
†
1[ ] [ [ [ [ 0 [
ADD dst, src
†
dst ← dst + src
0[ ] [ [ [ [ 0 [
AND dst, src
†
dst ← dst AND src
5[ ] – [ [ 0 – –
*Note: These instructions have an identical set of addressing modes, which are encoded for brevity. The
first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically
by a ‘[ ]’ in this table, and its value is found in the following table to the left of the applicable addressing
mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination)
and Ir (source) is 13.
UM001602-0904
Instruction Set