Z86E3016PSG Datasheet, PDF (313/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
295
Flag
C
Z
S
V
D
H
Description
Set if the bit rotated from the most significant bit position was 1 (
i.e., bit 7 was 1).
Set if the result is zero; cleared otherwise.
Set if the result in bit 7 is set; cleared otherwise.
Set if arithmetic overflow occurred (if the sign of the destination
operand changed during rotation); cleared otherwise.
Unaffected.
Unaffected.
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If the contents of Register C6h are 88h (10001000b), the statement:
RL C6h
Op Code: 80 C6
leaves the value 11h (00010001b) in Register C6h. The C and V Flags
are set, and the S and Z flags are cleared.
Example
If the contents of Register C6h are 88h, and the contents of Register 88h
are 44h (01000100b), the statement:
RL @C6h
Op Code: 81 C6
leaves the value 88h in Register 88h (10001000b). The S and V Flags
are set, and the C and Z flags are cleared.
UM001602-0904
Instruction Description