Z86E3016PSG Datasheet, PDF (171/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
153
Vectored Interrupt Cycle Timing
The interrupt acknowledge cycle time is 24 internal clock cycles and is
shown in Figure 102. In addition, two internal clock cycles are required
for the synchronizing flip-flops. The maximum interrupt recognition time
is equal to the number of clock cycles required for the longest executing
instruction present in the user program (assumes worst case condition of
interrupt sampling, Figure 95, just prior to the interrupt occurrence). To
calculate the worst case interrupt latency (maximum time required from
interrupt generation to fetch of the first instruction of the interrupt service
routine), sum these components:
Worst Case Interrupt Latency ≈ 24 INT CLK (interrupt acknowledge
time) + # T_PC of longest instruction present in the user's application pro-
gram + 2T_PC (internal synchronization time).
Internal Clock
AS
/DS
A0-A7 OUT
A0-A7 IN
Fetch
Fetch
M1
M2
M3
Stack Push Stack Push Stack Push Vector High Vector Low
M1
M2
For Stack External Only
Odd Vector Address
PC
PC+1
PC
SP-1 PCL SP-2 PCH SP-3 FLAGS
Even Vector Address
VECT VECT+1
Op Code (Discarded)
VECTH VECTL
First Instruction Of Interrupt Service Routine
R/W
For Stack External Only
Figure 102. Z8 Interrupt Acknowledge Timing
UM001602-0904
Interrupts