Z86E3016PSG Datasheet, PDF (79/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
61
I/O Ports
The Z8^® CPU features up to 32 lines dedicated to input and output. These
lines are grouped into four 8-bit ports known as Port 0, Port 1, Port 2, and
Port 3. Port 0 is nibble programmable as input, output, or address. Port 1
is byte configurable as input, output, or address/data. Port 2 is bit pro-
grammable as either inputs or outputs, with or without handshake and
SPI. Port 3 can be programmed to provide timing, serial and parallel
input/output, or comparator input/output.
All ports have push–pull CMOS outputs. In addition, the push–pull out-
puts of Port 2 can be turned off for open-drain operation.
Mode Registers
Each port has an associated Mode Register that determines the port’s
functions and allows dynamic change in port functions during program
execution. Port and Mode Registers are mapped into the Standard Regis-
ter File as shown in Figure 28.
UM001602-0904
I/O Ports