Z86E3016PSG Datasheet, PDF (166/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
148
Register FAh
Interrupt Request Register (IRQ)
(Read/Write)
D7 D6 D5 D4 D3 D2 D1 D0
0 = IRQ0 RESET
1 = IRQ0 SET
0 = IRQ1 RESET
1 = IRQ1 SET
0 = IRQ2 RESET
1 = IRQ2 SET
0 = IRQ3 RESET
1 = IRQ3 SET
0 = IRQ4 RESET
1 = IRQ4 SET
0 = IRQ5 RESET
1 = IRQ5 SET
Reserved /Int Edge Select
Figure 98. Interrupt Request Register
IMR is cleared before the IRQ enabling sequence to insure no unexpected
interrupts occur when EI is executed. This code sequence should be exe-
cuted prior to programming the application required values for IPR and
IMR.
IRQ bits 6 and 7 are device dependent. When reserved, the bits are not
used and will return a 0 when read. When used as the Interrupt Edge select
bits, the configuration options are as show in Table 21.
Interrupts
UM001602-0904