Z86E3016PSG Datasheet, PDF (208/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
190
Register F8h (P01M)
Port 0–1 Mode Register (P01M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P07 Mode
00 = Output
01 = Input
1X = A8–A11
P10–P17 Mode
00 = Byte Output
01 = Byte Output
10 = AD0-AD7
11 = High Impedance AD0–AD7,
A8–A15, AS, DS, R/W
P04–P07 Mode
00 = Output
01 = Input
1X = A12–A15
Figure 123. External Address Configuration
External Stacks
The Z8^® CPU architecture supports stack operations in either the Z8^®
Standard Register File or external data memory. A stack’s location is
determined by bit 2 in the Port 0–1 Mode Register (F8h). If bit 2 is set to
0, the stack is in external data memory (see Figure 124).
The instruction used to change the stack selection bit should not be imme-
diately followed by the instructions RET or IRET, because this will cause
indeterminate program flow. After a RESET, the internal stack is selected.
External Interface
UM001602-0904