Z86E3016PSG Datasheet, PDF (253/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
235
Clear
CLR dst
Instruction Format
OPC
dst
Cycles
6
6
OPC
(Hex)
80
81
Address
dst
R
IR
Operation
dst ← 0
The destination operand is cleared to 00h.
Flag
C
Z
S
V
D
H
Description
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If Working Register R6 contains AFh, the statement:
CLR R6
Op Code: B0 E6
UM001602-0904
Instruction Description