Z86E3016PSG Datasheet, PDF (261/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
243
Instruction
SBC
Carry
Before DA
1
1
Bits 7–4
Value
(Hex)
7–F
6–F
H Flag
Before DA
0
1
Bits 3–0
Value
(Hex)
0–9
6–F
Number
Added To
Byte
A0
9A
Car
After
1
1
If the destination operand is not the result of a valid addition or subtrac-
tion of BCD digits, the operation is undefined.
Flag
C
Z
S
D
H
Description
Set if there is a carry from the most significant bit; cleared
otherwise (see table above).
Set if the result is zero; cleared otherwise.
Set if result bit 7 is set (negative); cleared otherwise.
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the destination Working Register operand is specified by add-
ing 1110b (Eh) to the high nibble of the operand. For example, if Working
Register R12 (CH) is the destination operand, then ECh will be used as the
destination operand in the Op Code.
E
dst
Example
If addition is performed using the BCD value 15 and 27, the result should
be 42. The sum is incorrect, however, when the binary representations are
added in the destination location using standard binary arithmetic.
0001 0101 = 15h
+ 0010 0111 = 27h
0011 1100 = 3Ch
UM001602-0904
Instruction Description