Z86E3016PSG Datasheet, PDF (193/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
175
Transmitted Data
(No Parity)
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Start Bit
Eight Data Bits
Two Stop Bit
Transmitted Data
(With Parity)
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Figure 113. Transmitter Data Formats
Start Bit
Seven Data Bits
Odd Parity
Two Stop Bit
UART Reset Conditions
After a hardware reset, the SIO Register contents are undefined, and
Serial Mode and parity are disabled. Figures 114 and 115 show the binary
reset values of the SIO Register and its associated mode register P3M.
Register RF0h
Serial I/O Register (SIO)
(Read/Write)
UUUUUUUU
Serial Data (D₀ = LSB)
Figure 114. SIO Register Reset
UM001602-0904
Serial Input/Output