Z86E3016PSG Datasheet, PDF (110/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
92
1
2
3
DAV
(Input To Z8)
4
5
RDY
(Output From Z8)
Data on Port
(Input To Z8)
Valid Data
State 1.
State 2.
State 3.
State 4.
State 5.
Port 3 output is High, indicating that the I/O device is ready to accept data.
The I/O device puts data on the port and then activates the DAV input. This causes the data to be latched
.into the port input register and generates an interrupt request.
the Z8^® CPU forces the Ready (RDY) output Low, signaling to the I/O device that the data has been latched.
The I/O device returns the DAV line High in response to RDY going Low.
the Z8^® CPU RR software must respond to the interrupt request and read the contents of the port in order for t
handshake sequence to be completed. The RDY line goes High if and only if the port has been read and
DAV is High. This returns the interface to its initial state.
Figure 50. Z8 Input Handshake
I/O Ports
UM001602-0904