Z86E3016PSG Datasheet, PDF (165/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
147
The RAM Protect option is selected at ROM mask submission time or at
EPROM program time. If not selected or not an available option, this bit is
reserved and must be 0.
Interrupt Request Register Initialization
The Interrupt Request Register (IRQ), shown in Figure 98, is a read/write
register that stores the interrupt requests for both vectored and polled
interrupts. When an interrupt is made on any of the six, the corresponding
bit position in the register is set to 1. Bit 0 to bit 5 are assigned to interrupt
requests IRQ0 to IRQ5, respectively.
Whenever Power-On Reset (POR) is executed, the IRQ resister is reset to
00h and disabled. Before the IRQ register will accept requests, it must be
enabled by executing an ENABLE INTERRUPTS (EI) instruction.
Setting the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR, bit 7) will not enable the IRQ. Execution of the EI instruction is
required (see Figure 99).
For polled processing, IRQ must still be initialized by an EI instruction.
To properly initialize the IRQ register, the following code is provided.
CLR IMR
EI
DI
// Make sure vectored interrupts are disabled.
// Enable IRQ register, otherwise read only.
// Not required if interrupts were previously enabled.
// Disable interrupt heading.
Note: IRQ is always cleared to 00h and is read only until the first EI instruction,
which enables the IRQ to be read/write.
UM001602-0904
Interrupts