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| Z86E3016PSG Datasheet, PDF (129/348 Pages) Zilog, Inc. – Z86E3016PSG | |||
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Z8 CPU
User Manual
111
VDD
P
N
PIN
VDD
P
Autolatch
Open-Drain
OE
Data Out
Data In
N
G1
Figure 65. Simplified CMOS Z8 I/O Circuit
The operation of the autolatch circuit is straight-forward. Assume the
input pad is latched at +5V (logic 1). The inverter G1 inverts the bit, turn-
ing the P-channel FET ON and the N-channel FET OFF. The output of the
circuit is effectively shorted to VDD, returning +5V to the input. If the pad
is then disconnected from the +5V source, the autolatch will hold the
input at the previous state. If the device is powered up with the input ï¬oat-
UM001602-0904
I/O Ports
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