Z86E3016PSG Datasheet, PDF (213/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
195
outputs (A15–A8) remain stable throughout the machine cycle, regardless
of the addressing mode.
Data Strobe
The Z8^® CPU uses DS to time the actual data transfer. For Write opera-
tions (R/W = Low), a Low on DS indicates that valid data is on the AD7–
AD0 lines. For Read operations (R/W = High), the bus is placed in a high-
impedance state before driving DS Low, so the addressed device can put
its data on the bus. The Z8^® CPU samples this data prior to raising DS
High.
Extended Bus Timing
Some products can accommodate slow memory access time by automati-
cally inserting an additional software controlled state time (Tx). This
stretches the DS timing by two clock periods. Figures 128 and 129 illus-
trate extended external memory Read and Write cycles.
UM001602-0904
External Interface