Z86E3016PSG Datasheet, PDF (212/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
194
Clock
Machine Cycle
T1
T2
T3
A15-A8
AD7–AD0
A7–A0
A8-A15
D7–D0 OUT
AS
DS
R/W
DM
Write Cycle
Figure 127. External Memory Write Cycle
Address Strobe
All transactions start with AS driven Low and then raised High by the
Z8^® CPU. The rising edge of AS indicates that R/W, DM (if used), and
the address outputs are valid. The address outputs (AD7–AD0), remain
valid only during MnT1 and typically must be latched using AS. Address
External Interface
UM001602-0904