Z86E3016PSG Datasheet, PDF (296/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
278
Logical AND
AND dst, src
Instruction Format
OPC
OPC
OPC
dst src
src
dst
Cycles
6
6
OPC
(Hex)
42
43
Address
Mode
dst src
r
r
r
lr
dst
10
44
R
R
10
45
R
IR
src
10
46
R
IM
10
47 IR IM
Operation
dst ← dst AND src
The source operand is logically ANDed with the destination operand. The
AND operation results in a 1 being stored whenever the corresponding
bits in the two operands are both 1, otherwise a 0 is stored. The result is
stored in the destination operand. The contents of the source bit are not
affected.
Flag
C
Z
S
V
D
H
Description
Unaffected
Set if the result is zero; cleared otherwise
Set if the result of bit 7 is set; cleared otherwise
Always reset to 0
Unaffected
Unaffected
Note: Address modes R or IR can be used to specify a 4-bit Working Register. In
this format, the source or destination Working Register operand is speci-
Instruction Description
UM001602-0904