Z86E3016PSG Datasheet, PDF (67/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
49
Clock
SCLK
RESET
AS
DS
R/W
Program execution starts 5 to 10 clock cycles after internal RESET has
returned High. The initial instruction fetch is from location 000Ch.
Figure 22 illustrates reset timing.
First Machine Cycle
T1
Hold Low For 4 SCLK
Periods (Minimum)
First Instruction Fetch
Figure 22. Reset Timing
After a reset, the first routine executed should be one that initializes the
control registers to the required system configuration.
The RESET pin is the input of a Schmitt-triggered circuit. Resetting the
Z8^® CPU will initialize port and control registers to their default states.
To form the internal reset line, the output of the trigger is synchronized
with the internal clock. The clock must therefore be running for RESET
to function. It requires 4 internal system clocks after reset is detected for
the Z8^® CPU to reset the internal circuitry. An internal pull-up, combined
with an external capacitor of 1 uf, provides enough time to properly reset
the Z8^® CPU (see Figure 23). In some cases, the Z8^® CPU has an internal
POR timer circuit that holds the Z8^® CPU in reset mode for a duration
UM001602-0904
Reset