Z86E3016PSG Datasheet, PDF (140/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
122
M3
M1
M2
Mn
T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3
First Decrement Occurs
Four Clock Periods Later
TMR is Written, Counter/Timer
is Loaded
#03h is Fetched
Figure 75. Counting Modes
Prescaler Operations
During counting, the programmed clock source drives the 6-bit Prescaler
Counter. The counter is counted down from the value specified by bits of
the corresponding Prescaler Register, PRE0 (bit 7 to bit 2) or PRE1 (bit 7
to bit 2; see Figures 70 and 71). When the Prescaler Counter reaches its
end-of-count, the initial value is reloaded and counting continues. The
prescaler never actually reaches 0. For example, if the prescaler is set to
divide-by-three, the count sequence is:
3–2–1–3–2–1–3–2–1–3...
Each time the prescaler reaches its end of count a carry is generated, that
allows the Counter/Timer to decrement by one on the next timer clock
input. When the Counter/Timer and the prescaler both reach the end-of-
count, an interrupt request is generated (IRQ4 for T0, IRQ5 for T1).
Depending on the counting mode selected, the Counter/Timer will either
come to rest with its value at 00h (Single-Pass Mode) or the initial value
will be automatically reloaded and counting will continue (Continuous
Mode). The counting modes are controlled by bit 0 of PRE0 and bit 0 of
PRE1 (see Figure 75). A 0, written to this bit configures the counter for
Counters and Timers
UM001602-0904