Z86E3016PSG Datasheet, PDF (210/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
192
Register F7h (P3M)
Port 3 Mode Register
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Bits
Configuration
00 P33 = Input
P34 = Output
01 P33 = Input
P34 = DM
10 P33 = Input
P34 = DM
11 P33 = DAV1/RDY1 P34 = RDY1/DAV1
Figure 125. Port 3 Data Memory Operation
Bus Operation
Typical data transfers between the Z8^® CPU and external memory are
illustrated in Figures 126 and 127. Machine cycles can vary from six to 12
clock periods depending on the operation being performed. The notations
used to describe the basic timing periods of the Z8^® CPU are machine
cycles (Mn), timing states (Tn), and clock periods. All timing references
are made with respect to the output signals AS and DS. The clock is
shown for clarity only and does not have a specific timing relationship
with other signals.
External Interface
UM001602-0904