Z86E3016PSG Datasheet, PDF (155/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
137
Interrupts
The Z8^® CPU allows 6 different interrupts from a variety of sources; up
to four external inputs, the on-chip Counter/Timer(s), software, and serial
I/O peripherals. These interrupts can be masked and their priorities set by
using the Interrupt Mask and the Interrupt Priority Registers. All six inter-
rupts can be globally disabled by resetting the master Interrupt Enable, bit
7 in the Interrupt Mask Register, with a Disable Interrupt (DI) instruction.
Interrupts are globally enabled by setting bit 7 with an Enable Interrupt
(EI) instruction.
Register
7
Interrupt Mask
Interrupt Request
Interrupt Priority
HEX Identifier
FBh
IMR
FAh
IRQ
F9h
IPR
Figure 90. Interrupt Control Registers
There are three interrupt control registers: the Interrupt Request Register
(IRQ), the Interrupt Mask register (IMR), and the Interrupt Priority Regis-
ter (IPR). Figure 90 shows addresses and identifiers for the interrupt con-
trol registers. Figure 91 is a block diagram showing the Interrupt Mask
and Interrupt Priority logic.
UM001602-0904
Interrupts