Z86E3016PSG Datasheet, PDF (83/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
65
General I/O Mode
Port 0 can be an 8-bit, bidirectional, CMOS or TTL compatible I/O port.
These eight I/O lines can be configured under software control as a nibble
I/O port (P03–P00 input/output and P07–P04 input/output), or as an
address port for interfacing external memory. The input buffers can be
Schmitt-triggered, level shifted, or a single-trip point buffer and can be
nibble programmed. Either nibble output can be globally programmed as
push–pull or open-drain. Low EMI output buffers in some cases can be
globally programmed by the software as an OTP program option or as a
ROM mask option. In such cases, the Z8^® MCU features autolatches that
are hardwired to the inputs. Please refer to the specific Z8 MCU product
specification for the exact input/output buffer features that are available
(see Figures 30 and 31).
UM001602-0904
I/O Ports