Z86E3016PSG Datasheet, PDF (321/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
303
Set Register Pointer
SRP src
Instruction Format
OPC
src
Cycles
6
OPC
(Hex)
31
Address Mode
dst
IM
Operation
RP ← src
The specified value is loaded into the Register Pointer (RP) (Control Reg-
ister FDh). Bits 7-4 determine the Working Register Group. Bits 3-0
selects the Expanded Register Bank. Addressing of un-implemented
Working Register Group, while using Expanded Register Banks, will
point to Bank 0.
Example
SRP TD addresses Working Register Group 7 of Bank 0.
Register Pointer
(FDh)
Contents (Bin)
1111 0000
1110 0000
1101 0000
1100 0000
1011 0000
1010 0000
1001 0000
Working
Register
Group
(Hex)
F
E
D
C
B
A
9
Actual
Registers
(Hex)
F0–FF
E0–EF
D0–DF
C0–CF
B0–BF
A0–AF
90–9F
UM001602-0904
Instruction Description