Z86E3016PSG Datasheet, PDF (131/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 CPU
User Manual
113
V_DD
V_DD
A0
R_P
Data in
PIN
Logic 1
R_H
R_H
Data in
PIN
Logic 0
A0
R_P
Figure 66. Autolatch Equivalent Circuit
Design Considerations
For circuits in which the autolatch is active, consideration should be given
to the loading constraints of the autolatches. For example, with weak val-
ues of V_IN, close to Vih (min) or Vil (max), pullup or pull-down resis-
tances must be calculated using Ref = R/Rp. For best case STOP mode
operation, the inputs should be within 200 mV of the supply rails.
In output mode, if a port bit is forced into a tri-state condition, the auto-
latches will force the pad to V_DD. If there is an external pulldown resistor
on the pin, the voltage at the pin may not switch to GND due to the auto-
latch. As shown in Figure 67, the equivalent resistance of the autolatch
and the external pulldown form a voltage divider, and if the external resis-
tor is large, the voltage developed across it will exceed V_IL(max). For
worst case.
V_IL(max > V_DD [R_EXT ÷ (R_EXT + R_P)]
R_EXT(max) = [(V_IL(max) ÷ V_DD) R_P] ÷ [1—(V_IL(max) ÷ V_DD)]
For V_DD = 5.0 V and I_AO = 5 µA, V_IH(max) = 0.8 V:
R_EXT(max) = (0.16 ÷ 1M) ÷ (1—0.16) = 190 KΩ.
UM001602-0904
I/O Ports