Z86E3016PSG Datasheet, PDF (92/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
74
Register F6h
Port 2 Mode Register (P2M)
(Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
Port 2 Mode
0 = Output
1 = Input
Figure 38. Port 2 I/O Mode Configuration
General Port I/O
Port 2 can be an 8-bit, bidirectional, CMOS- or TTL- compatible I/O port.
These eight I/O lines can be configured under software control to be an
input or output, independently. Input buffers can be Schmitt-triggered,
level-shifted, or a single trip point buffer and may contain autolatches.
Bits programmed as outputs may be globally programmed as either push–
pull or open-drain. Low-EMI output buffers can be globally programmed
by the software, an OTP program option, or as a ROM mask option. In
addition, when the SPI is featured and enabled, P20 functions as data-in
(DI), and P27 functions as data-out (DO). Please refer to specific product
specifications for exact input/output buffer type features available. See
Figures 39 through 41.
I/O Ports
UM001602-0904