Z86E3016PSG Datasheet, PDF (198/348 Pages) Zilog, Inc. – Z86E3016PSG

Z8 Family of Microcontrollers
User Manual
180
and interrupt is generated. Before data is transferred via the D0 pin, the
SPI Enable bit in the SCON Register must be enabled.
SPI Compare
When the SPI Compare Enable bit, D3 of the SCON Register is set to 1,
the SPI Compare feature is enabled. The compare feature is only valid for
slave mode. A compare transaction begins when the (SS) line goes active.
Data is received as if it were a normal transaction, but there is no data
transmitted to avoid bus contention with other slave devices. When the
compare byte is received, IRQ3 is not generated. Instead, the data is com-
pared with the contents of the SCOMP Register. If the data does not
match, DO remains inactive and the slave ignores all data until the (SS)
signal is reset. If the data received matches the data in the SCOMP regis-
ter, then a SMR signal is generated. DO is activated if it is not tri-stated by
D2 in the SCON Register, and data is received the same as any other SPI
slave transaction.
Slaves’ not comparing remain in their current mode, whereas slaves’
comparing wake from a STOP mode by means of an SMR
SPI Clock
The SPI clock maybe driven by three sources: Timer0, a division of the
internal system clock, or the external master when in slave mode. Bit D6
of the SCON Register controls what source drives the SPI clock. A 0 in bit
D6 of the SCON Register determines the division of the internal system
clock if this is used as the SPI clock source. Divide by 2, 4, 8, or 16 is
chosen as the scaler.
Serial Input/Output
UM001602-0904